1. Field of the Invention
The invention relates to triacs.
Triacs are semiconductor components having two main electrodes and a control electrode (gate), this latter allowing the triac to be enabled so that current can pass between the main electrodes.
2. Description of the Prior Art
When the triac has been enabled by an appropriate pulse on its gate, it remains conducting until a zero cross over of the current which flows between its main electrodes, then it is disabled and should theoretically only be enabled again when a new pulse arrives on its gate.
The zero cross overs of the current between the main electrodes are imposed by the circuit external to the triac. In particular, triacs are used in circuits fed with alternating power, so as to control loads which may be either completely resistive or more or less inductive or capacitive. The control of more or less inductive loads is very frequent since it is met with particularly in the control of motors.
When the load is inducted, there is a phase delay between the current which flows through the load and the supply voltage at the terminals of this load. The result is that at the time of zero cross over of the current in the triac, the voltage at the terminals of the load is non zero (whereas it would be so with a purely resistive load).
Not only is this voltage not zero but it may be an appreciable fraction of the supply voltage.
Now, when the triac is disabled under the effect of cancellation of the current which flows through it, it acquires a very high impedance which means that substantially the whole of the supply voltage is to be found abruptly at the terminals of the triac and no longer at the terminals of the load.
There is then, at the time of disabling of the triac, a very rapid growth of the voltage at the terminals of the triac, which voltage passes in a very short time from 0 to a considerable fraction of the supply voltage. It is known that this very rapid growth may cause the triac to strike, that is to say untimely re-enabling (which will last until the next cancelling of the current in the load). This striking, called dV/dt striking is quite undesirable since the triac should only be re-enabled by gate pulses at well controlled times.
This phenomenon is all the more troublesome that dV/dt re-striking after a conduction phase seems to occur for a value of dV/dt (time growth gradient of the voltage) appreciably lower than the value which the triac would withstand if an attempt were made to cause dV/dt striking thereof without a previous conduction phase. In the presence of a previous conduction phase, the resistance of the components to such undesirable re-striking is called "dV/dt resistance to switching on opening";
It is therefore desirable to construct triacs which are insensitive to re-enabling by dV/dt striking on switching.
However, it is desirable for these triacs to be sensitive to a control provided by a low gate current.
These two requirements result in contradictory design constraints, all the more so since in general it is desirable to obtain triacs which are sufficiently sensitive whatever the polarities of the voltages at the terminals of the different electrodes of the triac.
It is recalled in this connection that the triggering of a triac is achieved in four distinct modes which are the following, in which a main electrode A1 is taken as potential reference, and the potential V2 of the other main electrode A2 and the potential Vg of the gate G are examined:
triggering in the first quadrant: V2 positive, Vg positive, triggering in the second quadrant: PA1 V2 positive, Vg negative, triggering in the third quadrant: PA1 V2 negative, Vg negative, triggering in the fourth quadrant: PA1 V2 negative, Vg positive. PA1 a type N central layer (N2), a first P type layer (P1) covering the central layer on the upper face side, PA1 a second P type layer (P2) covering the central layer on the lower face side, PA1 a first N type region (N1) formed in a part of the first P layer and being flush with the upper face in this part whereas the first P layer is flush with the rest of the upper face, the first N type region being moreover pierced with small so called emitter short circuit holes (CC1) through which the firt P layer P1 rises and is flush with the upper surface. PA1 a second N type region (N4) formed in another part of the first P layer and being flush with the upper face in this other part. PA1 a third N type region (N3) formed in a part of the second P layer (P2) and flush with the lower face in this part whereas the second P layer is flush with the rest of the lower face, the third N type region being moreover pierced with small so called emitter short circuit holes (CC3) through which the second P layer comes flush with the lower face. PA1 the first main electrode (A1) covering substantially the whole of the first N type region, including the short circuit holes of this first region, and covering a major flush part of the first P type layer, but not covering the first N type region and the first P type region in the immediate vicinity of the second N type region (N 4); PA1 the gate electrode covering substantially the whole of the second N type region (N4) as well as a small flush part (P'1) of the first P type layer, this small part being spaced apart from the major flush part of the first P type layer and being connected to this major part by a small narrow flush portion of the first P type layer, this narrow portion surrounding the second N type region and not being covered by an electrode; PA1 in this structure, the gate electrode is partially in line with a flush part of the second P type layer (P2) and partially in line with a part of the third N type region (N3).
Obtaining sufficient sensitivity for gate triggering in these four quadrants results in particular configurations of the different doped zones and metal electrodes which form the internal structure of the triac.
Prior Art FIGS. 1 to 3 shows a normal triac configuration with so called central gate.
To explain this structure, a cross section of the structure has been shown first of all in FIG. 1 then in FIG. 2 a top view showing the cutting up of the doped zones (spotted zones of type N or non spotted zones of type P, surrounded by fine lines) and cutting up of the electrodes A1 and G (hatched zones surrounded by thick lines), and finally in FIG. 3 a bottom view also showing cutting up of the doped zones and the lower electrode A2.
The doped semiconductor regions forming the triac are the regions N1, N2, N3, N4 of type N and P1, P2 of type P formed as a sandwich. In the figures, regions N are spotted so as to distinguish them from regions P which are not. In particular, in FIGS. 2 and 3 cutting up of zones N and P flush with the surface of the structure has been shown.
Region N2 is a central layer extending in the middle of the whole structure.
Region P1 covers the whole of region N2 on one side (upper face side).
Region P2 covers the whole of region N2 on the other side (lower face side).
Region N1 is formed at the surface of region P1 but substantially only in half of the structure (left hand half in the Figures); region N1 is flush with the semiconductor surface (upper face) where it exists. Region P1 is flush with the same surface where there is no region N1; in practice, small holes CC1 called emitter short circuits are formed in the region N1; these are holes through which region P1 rises to the surface in the zone where region N1 is generally present.
Region N3 is formed at the surface of region P2, substantially over a little more than half of the surface of the structure. Region N3 is flush with the surface (which forms the lower face) of the semiconductor structure where it is present. Region P2 is flush with the rest of the lower face. Emitter short circuit holes CC3 are distributed throughout the major part of region N3.
Region N4 is a small region equivalent to region N1, formed in the region P1 and flush with the same side as region N1 but located elsewhere and intended to be covered by the gate metallization. For a central gate triac, the region N4 is the center of the structure; for a corner gate triac it would be in a corner. In addition, region N4 is located in conventional triacs facing a portion or region N3 and more precisely facing a portion of zone N3 which does not have any short circuit holes CC3.
The metallization A2 covers substantially the whole of the rear face, namely the region N3 where it is present and region P2 over the rest of the surface.
The metallization A1 covers a large part of the front face, the remainder being covered by the gate metallization G, with a gap obviously provided between these metallizations so that there is no short circuit therebetween.
More precisely, metallization A1 covers the region N1 (including moreover the short circuit holes CC1 through which the region P1 rises to the surface) except for a small strip which is the portion of region N1 the closest to region N4. It also covers region P1 except for the small strip which is the portion of region P1 the closest to region N4.
Finally, the metallization G covers essentially the region N4 without extending over region P1 except in a small zone P'1 of region P1; this small zone P'1 covered by the metallization G is a zone which is placed apart from the major part of region P1 but which is not completely separated since it is connected thereto by a narrow strip P"1 of region P1 which is covered neither by the metallization A1 nor by the metallization G.
FIGS. 4 to 6, similar to Prior Art FIGS. 1 to 3, show the structure of a corner gate triac. The above description remains valid and the references of zones N to P are the same. It should be noted that FIG. 6 is not truly a bottom view; it is a reversed bottom view so that the facing zones correspond to each other. In other words, the corner at the bottom right of FIG. 5 is the gate zone which is opposite the bottom right corner of FIG. 5 (part of zone N3 without short circuit holes CC3). We may also say that FIG. 6 represents the lower face of the structure seen by transparency in the same direction as FIG. 5 (top view).
The triacs shown in FIGS. 1 to 6 have insufficient dV/dt resistance characteristics, more especially during application of abrupt voltage fronts after a conduction phase of the triac.